Automated testing is a critical step in the production of integrated circuit (IC) devices. Large scale IC manufacturers rely on highly sophisticated Automated Test Equipment (ATE) systems to test their devices, and the cost of these tests often comprises a significant percentage of the device cost.
FIG. 1A illustrates the main components of a typical present ATE system. The ATE system 100 includes an ATE unit 102 connected to a control computer 104. Control computer 104 provides a user interface that accepts input commands to the ATE unit 102 and outputs test results and other information. In system 100, a device under test (DUT) 108 is mounted on an adapter (or load) board 106. Adapter board 106 provides the physical and electrical interface between DUT 108 and ATE unit 102. The ATE unit 102 tests the DUT 108 by driving stimulus signals into the DUT and receiving responsive signals from the DUT. The correlation between these input and output signals is processed by the ATE unit to determine whether the DUT passed or failed the test.
The stimulus signals generated by the ATE unit 102 comprise data signals and clock signals to synchronize the stimulus input. The effectiveness of the test depends on the accurate placement of these signals relative to one another. For example, several different signals, such as, clock, data, and enable signals must be coordinated and triggered at appropriate times to ensure that meaningful data is acquired during the test process. Inaccuracy of clock and data signal edge placement will result in false test results. As the operating speed of devices to be tested increases, the margins of error for edge placement accuracy decreases.
The increasing performance of each new generation of IC's thus places greater demands on existing ATE systems. As a result, ATE vendors are increasingly forced to redesign or retrofit existing ATE systems to accommodate newer generation high speed devices. The adaptation of existing ATE systems to test new high speed devices, such as through parallel processing or increased software processing, leads to systems that are both expensive and inadequate for long-term test solutions.
A significant development in the design of new generation IC devices is the advent of high speed source synchronous bus interface devices. A notable example of such a device interface specification is the RAMBUST.TM. channel, which was developed to overcome the processor-to-memory performance gap resulting from the inability of memory devices to keep pace with the performance increases of microprocessors. RAMBUS is a trademark of Rambus, Inc. of Mountain View, Calif. The Direct RAMBUS Channel is a high performance device-to-device interface that enhances input/output transfers between devices. Current RAMBUS devices are capable of transferring data at up to 800 MHz, in contrast to the 100 to 200 MHz transfer rates of current DRAM (Dynamic Random Access Memory) devices.
The RAMBUS channel is a source synchronous bus interface in which a clock signal is transmitted alongside data to create a point-to-point bus interface, and all commands and data are referenced to clock edges. This type of interface more easily creates and maintains accurate clock-to-data relationships among devices, as opposed to common clock distribution methods where the clock-to-data relationships must be maintained by managing the skew of clock distribution trees. For a source synchronous bus interface, data exchanges originate from a source device, and terminate at a destination device. The proper clock-to-data timing relationship is established by the source device. The destination device receives both the clock and data, using the clock to properly capture the data sequence. Because of the high transfer rates, clock-to-data skew must be minimized to ensure that data transfers are properly synchronized.
Present known ATE systems are generally unable to accurately and inexpensively test devices developed for high performance interfaces such as the Direct RAMBUS Channel. When applied to Rambus Signaling Level input/output timing, the edge placement accuracy of an ATE system constitutes a significant portion of the specification that is to be measured. In general, edge placement accuracy in the context of ATE systems refers to the placement of data edges relative to clock trigger edges, and is affected by skew and jitter of the clock signal. Assuming that an ATE system is required to exhibit edge placement accuracy of on the order of ten percent of specification, present systems that are at best capable of edge placement accuracy of +/-50 picoseconds would not be accurate enough to test RAMBUS devices that are capable of attaining 800 MHz transfer rates.
FIG. 1B illustrates an interface between a memory controller and RAMBUS memory devices for a single-channel RAMBUS system. In circuit 150, a memory controller 152 is coupled to three RAMBUS in-line memory modules (RIMMs). Each RIMM module 154, 156, and 158 contains a number (typically four or eight) of RAMBUS DRAM (RDRAM) devices 166. Data signals 170 and address/control signals 172 are transmitted from the memory controller to the RIMM modules. The data and address/control signals are terminated to a termination voltage V.sub.term 162 through termination resistors 164. Clock 160 generates a clock signal with a phase alignment required by the memory controller 152. In a RAMBUS channel, data is transferred on both edges of the clock, thus a 400 MHz clock signal results in an 800 MHz transfer rate.
The clock loop begins at the termination end of the channel and propagates to the controller end as ClockToMaster (CTM) 176; it then loops back from the memory controller 152 as ClockFromMaster (CFM) 174 to the RIMM modules, and terminates through termination resistor 164. The clock and data signals travel in parallel to minimize skew, and their electrical lengths are equal to maintain the proper clock-to-data timing relationship at the destination device. Data is transmitted from the RIMMs to memory controller 152 synchronously with the CTM signal 176, and memory controller 152 sends data to the RIMMs synchronously with the CFM signal 174.
Present known ATE systems, such as ATE system 100 of FIG. 1A, exhibit several disadvantages when testing high speed source synchronous bus interface devices, such as RAMBUS RDRAMs. These systems are typically designed as general purpose systems that are intended to test a variety of different devices. The hardware interface between the DUT and test unit is often simplified to enhance this flexibility. Such systems rely on extensive software programming and user expertise to test a fill range of device types. Because such test systems are designed for general purpose use, the DUT is tested in an artificial environment in which all signals driving the DUT are derived from the ATE unit itself.
Although present ATE systems may attempt to simulate the operating conditions of a DUT, they are unable to accurately recreate the native environment of the DUT. Therefore, present ATE test environments typically do not accurately reflect the electrical and timing conditions of the native environment of the device, and thus do not always accurately account for the stresses encountered during normal operation.
Furthermore, present ATE systems typically perform pass/fail or marginality tests of a device only in comparison with a given specification. Such tests thus measure the performance of a device under artificial conditions and in reference to an absolute standard. Present ATE systems do not measure the margin of error for a device with regard to its tolerance under varying operational conditions that may be present in its native environment.
An additional disadvantage of present known ATE systems is that all data stimulus signals are driven from a clock circuit that is typically located a significant distance from the device under test. As a result, propagation delays and degradation of the clock signal due to noise limit the accuracy of these systems when testing high speed devices. Moreover, such ATE systems may also include multiple independent timing generators that further complicates distribution of clock signals to the DUT and increases the possibility of clock-data skew at the DUT.